The OpenRISC 1200-FT (Fault Tolerant) is equivalent to the OpenRISC 1200 processor (OR1200). Figure 1 illustrates the OR1200 processor debugging and verification framework.

The OR1200 processor debugging framework make use of the following tools:

• Compatible with both FPGA and ASIC targets through USB-JTAG interface
• RTL simulation debugging (Even Driven Simulation), Icarus, ModelSim, Silos
• Cycle accurate C-model simulator through Verilator (C-model created from Verilog RTL)
• Architecture C-model Simulator through Or1kSIM (C-model reference model)

Figure 1. Illustration of the OpenRISC 1200 processor debugging and verification framework.

The OR1200 processor verification framework offers extensive support for the industry standard GCC's complete regression test-suite.

• GNU C compiler, approximately 53,000 tests
• GNU C++ compiler, approximately 20,000 tests
• GNU C++ library, approximately 3,000 tests
• GNU Debugger, approximately 10,000 tests

To conclude, the OR1200 processor debugging and verification framework offer approximately 86,000 tests. This allows the OR1200 and OR1200-Fault Tolerant to be a very thouroghly tested processor. The tests can be executed for all four options:

• Target FPGA/ASIC debugging
• Event Driven Simulation
• System C simulation
• Or1kSIM simulation

These methods can be applied on larger systems, allowing verification of complex System-on-Chip (SoC) designs.