The PIC16-FT (Fault Tolerant) is compatible with the Microchip PIC16F84 device. The orgininal development RTL can be downloaded from opencores.org. However, Ã…AC has made significant improvements to the processor core, including fixing several major bugs. This core was developed in order to have a minimalistic processing capability in very power efficient modules, where only limited computational performance is demanded. This core is used in the Ã…AC nanoRTUâ„¢ 200 series of devices. Figure 1 illustrates the PIC16 processor architecture and implementation. The PIC16-FT incorporates the following:

• 14 bit instructions Micro Control Unit (MCU)
• 68 byte of data RAM
• 4 times faster than normal, fully pipelined,1 instruction / clock, (nominal on PIC is 1 instruction / 4 clocks)
• Extended program memory to 4,000 words (nominal on PIC's is 1,000)
• Supporting two 8 bit Ports (A & B)
• Supporting timer interrupt
• Supporting one external interrupt that can be multiplexed and masked to support multiple interrupts

Figure 1. Illustration of the PIC16-FT processor architecture.

Ã…AC PIC16-FT IP library

Ã…AC have adapted many interfaces for the PIC16-FT softcore processor. The current available verified and supported IP blocks compatible with the Ã…AC arbiter, "aBone" interface are shown in Figure 2. All IP blocks have full support in the Ã…AC PIC16-FT C API library. A detailed list of the IP is given here:

• aBone (Ã…AC arbiter)
• Debug interface with direct memory control (writing to EEPROM/Memory without having the processor running)
• Interrupt extender (providing interrupts for I2C, SCET, UART, Fault detection Error manager)
• EEPROM memory controller (I2C) with boot support
• User memory mapped RAM block
• High speed UART (up to 1 Mbps)
• SPI master interface
• I2C master/slave interface
• GPIO interface
• Watch dog
• System Elapsed Time (SCET) timer interface

Figure 2. Illustration of the available verified and supported IP blocks for PIC16-FT.

Performance figures / Implementation information

General performance for PIC16 CPU core,

• 16 MIPS at 16 MHz system clock

FPGA performance

• ACTEL ProAsic A3P family: TBD core cells, TBD FF, TBD block RAM