The OpenRISC 1200-FT (Fault Tolerant) is equivalent to the OpenRISC 1200 processor (OR1200). Figure 1 illustrates the OR1200 processor architecture and implementation. You can read and download the entire processor documentation from opencores.org website. The OR1200 is highly configurable and support the following (DSP, FPU, MMU, Cache sizes can be switched on/off):

• 32 bit Central Processing Unit (CPU) and DSP (MUL/DIV MAC)
• Compatible with 32 bit load / store RISC architecture
• Scalar, single-issue 5-stage pipeline
• Direct mapped Instruction (I) and Data (D) cache
• Memory Management Unit (MMU)
• Power management unit
• Interrupt Controller (32 interrupts)
• Tick Timer Unit
• Dual WISHBONE interfaces
• Optional user customizable instructions.
• IEEE 754 compliant single and/or double precision floating point unit (FPU)
• Debug interface

Figure 1. Illustration of the OpenRISC 1200 processor architecture.

Specification document for OpenRISC 1200 is available in Adobe PDF, MS Word, and Open Office formats:

• English OpenRISC 1000 Architecture (PDF, 1.5MB)
• English OpenRISC 1200 Specification (PDF, 450KB)
• English OpenRISC 1200 Supplementary Programmer's Reference Manual (PDF)
• Japanese OpenRISC 1200 Specification (PDF, by Takashi Okawa).

Ã…AC OpenRISC 1200-FT IP library

Ã…AC have verified many extensions to the OpenRISC 1200-FT processor. The current verified and supported IP blocks are all Wishbone B3 compatible and is illustrated in Figure 2. All IP blocks have full support in the Ã…AC supported LINUX 2.6.36 kernel and Ã…AC OpenRISC 1200-FT C API library (for non-MMU configuration).  A detailed list of the supported IP blocks is given here:

• Wishbone B3 interface
• SDRAM memory controller (PC133)
• Ethernet 10/100/1000 MAC
• SpaceWire and router (n ports)
• USB 1.1 Host/Slave
• CAN 2.0B
• 16550 Compatible UART
• General Purpose IO (GPIO)
• SPI master
• I2C master/slave
• System Elapsed Time (SCET)
• Watchdog

Figure 2. Illustration of the available verified and supported IP blocks for OpenRISC 1200-FT.

Performance figures / Implementation information

General performance for OR1200 CPU core,

• 20 Dhrystone MIPS at 20 MHz system clock
• 1.25 CoreMark / MHz (CoreMark 1.0)

FPGA performance

• ACTEL ProAsic A3P family: 15.000 core cells, 1850 FF, 48 block RAM, 25 MHz system clock
• Xilinx Virtex 5: 4.000 LUT, 7 block RAM, 70 MHz system clock